Non-volatile memories are commonly used in several applications in which the data stored in the memory device needs to be preserved even in the absence of a power supply. Within the class of non-volatile memories, electrically programmable (and erasable) memories, such as flash memories, have become very popular in applications in which the data to be stored is not immutable (e.g., in the case of a consolidated code for a microprocessor), but it is instead necessary from time to time to store new data, or to update the data already stored.
Typically, the memory device includes an arrangement of memory cells, disposed for example in rows and columns, so as to form a matrix.
Depending on the way the memory cells in the matrix are interconnected, two classes of flash memories can be identified: those having a NOR architecture (or “NOR flash memories”), and those having a NAND architecture, (referred to as “NAND flash memories”). Roughly speaking, in a NOR architecture the memory cells of the same matrix column are connected in parallel to the same bitline, whereas in a NAND architecture groups of memory cells of the same matrix column are serially interconnected so as to form strings, which strings are then connected in parallel to each other to the same bitline.
Compared to NOR flash memories, NAND flash memories are more compact (a lower number of contacts in the matrix are required), and they are also better suited for applications such as file storage.
In the NAND architecture, the memory space is ideally partitioned into a plurality of memory pages, with each page corresponding to a block of memory cells that, in operation, are read or written simultaneously, i.e., in parallel to each other. The number of memory cells in each block determines the size (i.e., the number of bits) of the memory page. Nowadays, memory pages of 512 bytes are rather typical, but larger memory pages are also encountered, for example of 2 KB.
Clearly, the memory cannot have so high a number of Input/Output (“I/O”) terminals as to enable transferring in parallel of so long of data words; usually, eight or sixteen I/O terminals are in fact provided. Thus, some kind of “segmentation” of the memory page is necessary for interfacing the memory with the outside world.
For this purpose, a circuit arrangement called “page buffer” is provided in the memory for managing the operations of reading the information stored in the memory cells of a selected memory page, or writing new information thereto. In very general terms, the page buffer includes a buffer register of size equal to that of the memory page, in which data read (in parallel) from the memory cells of a selected page are temporarily stored, before being serially outputted in chunks of, e.g., eight or sixteen bits, depending on the number of I/O terminals of the memory. Similarly, when data are to be written into the memory, the page buffer is replenished with data received serially in the eight- or sixteen-bit chunks, and, when the buffer has eventually been filled, the data are written in parallel into the memory cells of a given, selected memory page.
The page buffer includes a relatively high number of volatile storage elements, typically bi-stable elements or latches; the number of latches is proportional (in particular, equal) to the size (in number of bits) of the memory page. Thus, the page buffer is a circuit block that needs to be carefully designed (both at the circuit and at the physical layout level), so as to ensure that it does not occupy too large a semiconductor area, and it is efficient, particularly from the power consumption viewpoint.
If the operations to be performed on the memory cells are simply a “PAGE READ” (an operation involving reading data from a selected memory page) and a page write or “PAGE PROGRAM” (writing data into a selected memory page), the page buffer may in principle include a single register, with a number of latches equal to the size (in bits) of the memory pages. However, more complex operations may be desirable and required, and in these cases the structure of the page buffer may need to be upgraded. For example, in some applications it might be necessary that the memory is capable of performing operations such as a “COPY-BACK PROGRAM” and a “CACHE PROGRAM”. In a CACHE PROGRAM operation, data to be written into a memory page can be loaded into the page buffer while another memory page is still being written with data previously loaded in the page buffer; in this way, the time necessary for programming different memory pages in sequence is reduced. A COPY-BACK PROGRAM operation is instead exploited for copying the data contained in a given memory page into another memory page, in a way that is managed completely internally to the memory, without the necessity of outputting the data. A page buffer adapted to implement these two additional operations needs to include a pair of buffer registers (and thus two arrays of latches) that can be coupled to two selectable packets of bit lines of the matrix. In this case, the requirements of careful design of the page buffer are even stricter.
There has been identified some problems affecting the known page buffers.
As mentioned above, the latches making up the registers in the page buffer are volatile storage elements, and such elements, in a simple but common practical implementation, are formed by two CMOS inverters connected to each other so as to form a loop, i.e., with the output of one inverter connected to the input of the other. In a generic program operation (either a PAGE PROGRAM or a CACHE PROGRAM or COPYBACK PROGRAM), a generic bit of the data word to be written into a selected memory cell is first loaded into the latch, and then the content of the latch is transferred onto the selected bitline by activating an electrical connection of the latch output to the bitline (normally, selection pass MOSFETs are used to this end). The bitline normally has associated therewith a relatively high stray capacitance, which is typically on the order of some picofarads, and is normally precharged to a program inhibition voltage. When the latch output is connected to the bitline, a charge sharing takes place, whereby the charge stored in the bitline capacitance and in a parasitic capacitance associated with the latch output is redistributed between such two capacitances. The latch output capacitance is however far smaller than the bitline capacitance (in a typical design, the latch output capacitance may be on the order of some femtofarads, i.e., roughly three orders of magnitude lower than the bitline capacitance). The result of the charge sharing is that the bitline capacitance may easily prevail over the driving capability of the latch, and the voltage at the latch output vary depending on the bitline voltage. This may cause the latch to be incapable of driving the bitline in a way that is sufficient to cause the programming into the desired state of the selected memory cell (the latch is not capable of bringing the bitline from the initial, program inhibition voltage to a voltage adapted to cause programming of the selected memory cell) and, in the worst cases, the latch may even be caused to switch, with the consequence that the data bit stored in the latch is modified.
A similar problem is experienced during a read operation (such as a PAGE READ). In this case, the generic latch of the page buffer register, after having been loaded with the data bit read from the selected memory cell, is connected to a data line for transporting the data bit from the page buffer latch to output buffer circuits and then to the I/O terminal of the memory. The data line, similarly to the bitline, usually has associated therewith a relatively high stray capacitance, substantially higher than the latch output capacitance. Thus, the charge sharing between the latch output capacitance and the data line parasitic capacitance may easily cause the latch to be incapable of properly driving the data line, or even to switch and lose the stored data bit.
It is observed that the problems described above are experienced both in the case in which the page buffer includes only one register, and in cases of more complex page buffers, with two (and possibly more) registers.